Prior art processors and computer systems may be limited in the number of accesses to a particular cache or group of caches that can be concurrently managed. One prior art technique used to ameliorate this limitation has been the use of an inclusive cache structure whose cache entries correspond to the cache entries of one or more processor core-specific caches, such as level 1 (L1) caches. In other words, prior art multi-core processors and/or multi-processor computer systems have attempted to reduce cache access traffic to core caches by simply directing some of the cache accesses to a shared inclusive cache structure, such as a last level cache (LLC), that contains all of the cache entries of the processor cores or agents to which the inclusive cache structure corresponds. In the case of a cache access from a core within a multi-core processor, however, the core will typically attempt to access data first from its own cache and then resort to the shared cache. The shared inclusive cache structure is sometimes referred to as a “snoop filter” because it shields core caches from excessive cache accesses, and therefore traffic, from other agents by providing the requested data to these agents from the inclusive cache instead of the core's cache.
The prior art technique of using a cache structure, such as an LLC, for servicing cache requests from various agents is helpful in allowing requesting agents to obtain the data they need without resorting to a cache of a processor core, for example, if the data is not exclusively owned or modified by a particular processor core. To the extent that an agent, such as a processor or processor core owns the cache line of its cache in a shared state that the requesting agent is trying to access, a cache structure, such as an LLC, can allow the requesting agent to obtain the data it is requesting rather than waiting for the owning agent to share the data.
However, conflicts can occur when using an LLC to service cache requests. FIG. 1, for example, illustrates three events occurring at substantially the same time: core 0 attempts to access a cache line in the LLC that is exclusively owned by core 1; shortly thereafter, the LLC performs a capacity eviction of the accessed line from the LLC; about this time, core 1 initiates a writeback of that cache line. In some cases, as part of the LLC's capacity eviction sequencing, a snoop may need to be done to core 1 (a “back invalidation”) to preserve the LLC's inclusive property. Core 0 may retrieve erroneous data from the inclusive LLC if core 0's request is not properly reconciled with the writeback data from core 1 and, potentially, with data retained by core 1 after its writeback has taken place. Fulfilling the request of core 0 requires resolution of a three-way conflict between core 0's request, the LLC capacity eviction's back invalidate to core 1, and core 1's writeback of updated data.
The prior art problem depicted in FIG. 1 is exacerbated as the number of processor cores or other agents increases in the system. For example, the conflicts depicted in FIG. 1 may double in a multi-core processor containing four cores instead of the two illustrated in FIG. 1. Similarly, as the number of processors increase in a computer system, so does the potential number of accesses to any particular core cache, thereby increasing the number of conflicts that can occur during an LLC eviction.
Cache conflicts, such as those depicted in FIG. 1, can have adverse effects on processor performance because requesting agents either wait for the LLC eviction and corresponding back invalidates to complete, or detect and recover from retrieving incorrect data as a result of the conflict. Accordingly, the number of agents that may access a particular cache structure can be limited in prior art processor and/or computer systems.